A variety of different signalling techniques are used to transmit electronic signals over transmission media between electronic components. One technique that is used is called Low Voltage Differential Signalling (LVDS), which allows signals to be transmitted at very high frequencies over inexpensive, twisted-pair copper cables. In computer devices, LVDS is used for signalling over computer networks and internally in machines over computer buses.
LVDS is a differential signalling system, so that it uses the difference in voltages between two wires to signal information. The cost of two conductors or wires to convey the signal is offset by the gain in noise tolerance in the form of common-mode rejection, i.e., the same noise will be on both wires and so will cancel, leaving the difference. Since signal to noise rejection has been improved, the signal swing can be dropped to only a few hundred millivolts. The small swing enables faster data rates since the rise time is now shorter.
In an LVDS system, two different voltages are transmitted and are compared at the receiver. For example, the transmitter can inject a small current, such as 3.5 milliamperes, into one wire or the other, depending on the logic level to be sent. The current passes through a termination resistor at the receiving end, then returns in the opposite direction along the other wire. The receiver senses the polarity of the voltage difference across the resistor and uses this differential voltage to determine the logic level. Since only a small amplitude is used for the signal, the effects of capacitance and inductance are much reduced, as is the amount of radiated electromagnetic noise. The low differential voltage, typically on the order of 350 mV, causes LVDS to consume very little power compared to other systems, and this can be maintained at high frequencies due to the low voltage swing.
One problem with prior LVDS systems is that there is not an efficient way to provide a distinct clock signal as well as a data signal on a single transmitted signal. For example, a typical technique uses a serializer-deserializer (serdes) in a coding scheme such as 8B/10B encoding. In such encoding, two additional bits are added to provide and maintain sufficient state changes in the signal for the receiver to extract a clock signal embedded on the data signal using, for example, a phase-locked loop. However, this means that an extra two bits are transmitted for every byte, creating a reduced data rate and inefficiencies in the transmission. Furthermore, additional electronic components are needed to extract the clock signal.
Accordingly, what is needed is a method and system for providing an LVDS transmission system that can embed a second signal, such as a clock signal, on a data signal with greater data rate than in prior systems, and in which the solution is simple and inexpensive to implement. The present invention addresses such a need.